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| May 2001 Preliminary (R) 3.3V 2M x 8/1M x 16 CMOS synchronous DRAM Features * Organization - 1,048,576 words x 8 bits x 2 banks (2M x 8) 11 row, 9 column address - 524,288 words x 16 bits x 2 banks (1M x 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0 * All signals referenced to positive edge of clock, fully synchronous * Dual internal banks controlled by A11 (bank select) * High speed - 143/125/100 MHz - 7/8/10 ns clock access time * Auto refresh and self refresh * PC100 functionality * Automatic and direct precharge including concurrent autoprecharge * Burst read, write/Single write * Random column address assertion in every cycle, pipelined operation * LVTTL compatible I/O * 3.3V power supply * JEDEC standard package, pinout and function - 400 mil, 44-pin TSOP 2 (2M x 8) - 400 mil, 50-pin TSOP 2 (1M x 16) * Low power consumption - Active: 576 mW max - Standby: 7.2 mW max, CMOS I/O * 2048 refresh cycles, 32 ms refresh interval * 4096 refresh cycles, 64 ms refresh interval * Read/write data masking * Programmable burst length (1/2/4/8/ full page) * Programmable burst sequence (sequential/interleaved) * Programmable CAS latency (1/2/3) Pin arrangement TSOP 2 VCC DQ0 VSSQ DQ1 VCCQ DQ2 VSSQ DQ3 VCCQ NC NC WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VSS DQ7 VSSQ DQ6 VCCQ DQ5 VSSQ DQ4 VCCQ NC NC DQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 VSSQ DQ2 DQ3 VCCQ DQ4 DQ5 VSSQ DQ6 DQ7 VCCQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TSOP 2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VCCQ DQ11 DQ10 VSSQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS Pin designation Pin(s) DQM (2M x 8) UDQM/LDQM (1M x 16) A0 to A10 A11 DQ0 to DQ7 (2M x 8) DQ0 to DQ15 (1M x 16) RAS CAS WE CS VCC, VCCQ VSS, VSSQ CLK CKE Description Output disable/write mask RA0 - 10 Address inputs CA0 - 7 (x16) CA0 - 8 (x8) Bank address (BA) Input/output Row address strobe Column address strobe Write enable Chip select Power (3.3V 0.3V) Ground Clock input Clock enable AS4LC2M8S1 and AS4LC2M8S0 LEGEND Configuration Refresh Count Row Address Bank Address Column Address 2M x 8 1M x 8 x 2 banks 2K/4K (A0 - A10) 2 (BA) 512 (A0 - A8) Selection guide Symbol Bus frequency (CL = 3) Maximum clock access time (CL = 3) Minimum input setup time Minimum input hold time Row cycle time (CL = 3, BL = 1) Maximum operating current ([x16], RD or WR, CL = 3), BL = 2 Maximum CMOS standby current, self refresh 5/21/01; v.1.1 AS4LC1M16S0 and AS4LC1M16S1 1M x 16 512K x 16 x 2 banks 2K/4K (A0 - A10) 2 (BA) 256 (A0 - A7) -7 143 5.5 2 1.0 70 130 1 -8 125 6 2 1.0 80 100 1 -10 100 6 2 1.0 80 100 1 P. 1 of 29 Unit MHz ns ns ns ns mA mA fMax tAC tS tH tRC ICC1 ICC6 Alliance Semiconductor Copyright (c)Alliance Semiconductor. All rights reserved. AS4LC2M8S1 AS4LC1M16S1 (R) Functional description The AS4LC2M8S1, AS4LC2M8S0, and AS4LC1M16S1, AS4LC1M16S0 are high-performance 16-megabit CMOS Synchronous Dynamic Random Access Memory (SDRAM) devices organized as 1,048,576 words x 8 bits x 2 banks (2048 rows x 512 columns) and 524,288 words x 16 bits x 2 banks (2048 rows x 256 columns), respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data (512 bytes for 2M x 8 and 256 bytes for 1M x 16) without selecting a new column address. The operational advantages of an SDRAM are as follows: (1) the ability to synchronously output data at a high clock frequency with automatic increments of column-address (burst access); (2) bank-interleaving, which hides precharge time and attains seamless operation; and (3) the capability to change column-address randomly on every clock cycle during burst access. This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of applications. SDRAM commands and functions are decoded from control inputs. Basic commands are as follows: * Mode register set * Select column; write * Auto precharge with read/write * Deactivate bank * Select column; read * Self-refresh * Deactivate all banks * Deselect; power down * Select row; activate bank * CBR refresh Both devices are available in 400-mil plastic TSOP type 2 package. The AS4LC2M8S1/ AS4LC2M8S0 have 44 pins, and the AS4LC1M16S1/ AS4LC1M16S0 have 50 pins. All devices operate with a power supply of 3.3V 0.3V. Multiple power and ground pins are provided for low switching noise and EMI. Inputs and outputs are LVTTL compatible. Logic block diagram CLK Clock generator CKE A11 A[10:0] Bank select Row address buffer Mode register Refresh counter Row decoder Bank A 512K x 16 (2048 x 256 x 16) Bank B 512K x 16 (2048 x 256 x 16) Sense amplifier DQMU/DQML Command decoder CS RAS CAS WE Latch circuit Column address buffer Burst counter Input and output buffer Control logic Column decoder and latch circuit Data control circuit DQ For AS4LC2M8S1/AS4LC2M8S0, Banks A and B will read 1M x 8 (2048 x 512 x 8). 5/21/01; v.1.1 Alliance Semiconductor P. 2 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Pin descriptions Pin CLK Name System clock Description All operations synchronized to rising edge of CLK. Controls CLK input. If CKE is high, the next CLK rising edge is valid. If CKE is low, the internal clock is suspended from the next clock cycle and the burst address and output states are frozen. If both banks are idle and CKE goes low, the SDRAM will enter power down mode from the next clock cycle. When in power down mode and CKE is low, no input commands will be acknowledged. To exit power down mode, raise CKE high before the rising edge of CLK. Enables or disables device operation by masking or enabling all inputs except CLK, CKE, UDQM/LDQM (x16), DQM (x8). Row and column addresses are multiplexed. Row address: A0~A10. Column address (2M x 8): A0~A8. Column address (1M x 16): A0~A7. Memory cell array is organized in 2 banks. A11 selects which internal bank will be active. A11 is latched during bank activate, read, write, mode register set, and precharge operations. Asserting A11 low selects Bank A; A11 high selects Bank B. Command inputs. RAS, CAS, and WE, along with CS, define the command being entered. Controls I/O buffers. When DQM is high, output buffers are disabled during a read operation and input data is masked during a write operation. DQM latency is 2 clocks for Read and 0 clocks for Write. For x16, LDQM controls the lower byte (DQ0 - 7) and UDQM controls the upper byte (DQ8 - 15). UDQM and LDQM are considered to be in the same state when referred to jointly as DQM. Data inputs/outputs are multiplexed. Power and ground for core logic and input buffers. Power and ground for data output buffers. CKE Clock enable CS Chip select A0~A10 Address A11 Bank select RAS CAS WE Row address strobe Column address strobe Write enable x8: DQM x16: UDQM, LDQM Output disable/ write mask DQ0~DQ15 VCC/VSS VCCQ/VSSQ Data input/output Power supply/ground Data output power/ground 5/21/01; v.1.1 Alliance Semiconductor P. 3 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Operating modes Command Mode register set Auto refresh Entry Self refresh Bank activate Read Write Burst stop Precharge Selected bank Both banks Entry Exit Entry Precharge power down mode Exit DQM No operation command * V = Valid. CKEn-1 CKEn H H H L H H H H H H L H L H H X H L H X X X X X L H L H X X CS L L L L H L L L L L H L X H L H L X H L RAS L L L H X L H H H L X V X X H X H X X H CAS L L L H X H L L H H X V X X H X H X X H WE L H H H X H H L L L X V X X H X H X X H DQM X X X X X X X X X X X X X X X X X V X X A11 A10 Op code X X X X A9-A0 Note 1,2 3 3 3 3 4 4,5 4 4,5 6 Exit V* V V row address L H L H X L H X column address column address Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable V X X Clock suspend or active power down X X X X X 7 1 2 3 4 5 6 7 OP= operation code. A0~A11 see page 5. MRS can be issued only when both banks are precharged and no data burst is ongoing. A new command can be issued 2 clock cycles after MRS. Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after both banks are precharged. A11: bank select address. If low during read, write, row active and precharge, bank A is selected. If high during those states, bank B is selected. Both banks are selected and A11 is ignored if A10 is high during row precharge. A new read/write/deac command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after tRP from the end of the burst. Burst stop command valid at every burst length except full-page burst. DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). 5/21/01; v.1.1 Alliance Semiconductor P. 4 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Mode register fields Address Function A11~A10 RFU Register programmed with MRS A9 A8 A7 A6 A5 A4 WBL TM CAS latency A3 BT A2 A1 A0 Burst length RFU = 0 during MRS cycle. Write burst length A9 Length Programmed 0 burst length 1 Single burst A3 0 1 Burst type Type Sequential Interleaved A8 0 0 1 1 A7 0 1 0 1 Test mode Type Mode register set Reserved Reserved Reserved CAS latency A4 Latency 0 Reserved 1 1 0 2 1 3 X Reserved Burst length A0 BT = 0 0 1 1 2 0 4 1 8 0 Reserved 1 Reserved 0 Reserved 1 Full page A6 0 0 0 0 1 A5 0 0 1 1 X A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 BT = 1 1 2 4 8 Reserved Reserved Reserved Reserved Burst sequence (burst length = 4) Initial address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 Sequential 1 2 2 3 3 0 0 1 Interleave 3 0 1 2 0 1 2 3 1 0 3 2 2 3 0 1 3 2 1 0 Burst sequence (burst length = 8) A2 0 0 0 0 1 1 1 1 Initial address A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 4 5 5 6 6 7 7 0 0 1 1 2 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 4 2 5 1 6 0 7 7 0 6 1 5 2 4 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 5/21/01; v.1.1 Alliance Semiconductor P. 5 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Recommended operating conditions Parameter Supply voltage Input voltage Output voltage Ambient operating temperature Symbol VCC,VCCQ GND VIH VIL VOH VOL TA Min 3.0 0.0 2.0 -0.3 2.4 - 0 Nominal 3.3 0.0 - - - - Max 3.6 0.0 VCC + 0.3 0.8 - 0.4 70 Unit V V V V V V C Notes 8 8 VIL Min = -1.5V for pulse widths less than 5 ns. IOH = -2mA, and IOL = 2mA. Recommended operating conditions apply throughout this document unless otherwise specified. Absolute maximum ratings Parameter Input voltage Power supply voltage Storage temperature (plastic) Power dissipation Symbol VIN,VOUT VCC,VCCQ TSTG PD Min -1.0 -1.0 -55 - Max +4.6 +4.6 +150 1 Unit V V C W Notes - 50 mA Short circuit output current IOUT Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5/21/01; v.1.1 Alliance Semiconductor P. 6 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) DC electrical characteristics -7 Parameter Input leakage current Output leakage current Operating current (one bank active) Precharge standby current (power down mode) Precharge standby current (non-powerdown mode) Active standby current (powerdown mode) Active standby current (non-powerdown mode, one bank active) Symbol IIL IOL ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test conditions 0V VIN VCC, Pins not under test = 0V DOUT disabled, 0V VOUT VCCQ tRC min, IO = 0mA, burst length = 1 CKE VIL(max), tCK = 15 ns CKE and CLK VIL(max), tCK = CS VIH(min), CKE VIH(min), tCK = 15 ns; input signals changed once during 30 ns CLK VIL(max), CKE VIH(min), tCK = ; input signals stable CKE VIL(max), tCK = 15 ns CLK, CKE VIL(max), tCK = CKE VIH(min), CS VIH(min), tCK = 15 ns; input signals changed once during 30 ns CKE VIH(min), CLK VIL(max), tCK = ; input signals stable IO = 0 mA Page burst All banks activated tCCD = tCCD(min) tRC tRC(min) CKE 0.2 V CL =3 CL =2 CL =1 CL =3 -8 -10 Min Max Min Max Min Max Unit Notes -5 +5 -5 +5 -5 +5 A -10 +10 -10 +10 -10 +10 A - - - - 140 2.0 2.0 30 - - - - 100 2.0 2.0 30 - - - - 100 mA 2.0 mA 2.0 mA 30 mA 1,2,3 1,3, 4,5 - - - - 6 2 2 35 - - - - 6 2 2 35 - - - - 6 2 2 35 mA 1,2,3 mA 1,2,3 mA 1,2,3 mA 1,2,3 - 10 140 125 80 100 2 1 - - - - - - - 10 130 115 70 90 2 1 - - - - - - - 10 120 mA 1,2,3 Operating current (burst mode) ICC4 100 mA 70 80 2 1 mA mA mA 1,2, 3,5 1,2, 3,5 15 Refresh current Self refresh current CL = CAS latency. ICC5 ICC6 5/21/01; v.1.1 Alliance Semiconductor P. 7 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) AC parameters common to all waveforms Sym tAC Parameter CLK to valid output delay CAS latency 3 2 1 -7 Min - - - - 2 0 1 1 2.75 7 8.7 20 1 1 2 2.75 1 2 3 2 1 5 5 4 1 2 1 0 2 2 0 3 2 1 - - - 1 Max 5.5 8.5 18 1 - - - - - 1000 1000 1000 - - - - - - - - - - - - - - - - 5.5 8.5 18 - Min - - - - 2 0 1 1 3 8 10 25 1 1 2 3 1 2 5 5 4 1 2 1 0 2 2 0 - - - 1 -8 Max 6 7 22 1 - - - - - 1000 1000 1000 - - - - - - - - - - - - - - - - 6 9 22 - Min - - - - 2 0 1 1 3 10 12 25 1 1 2 3.5 1 2 5 5 4 1 2 1 0 2 2 0 - - - 1 -10 Max 6 6 22 1 - - - - - 1000 1000 1000 - - - - - - - - - - - - - - - - 9 9 22 - Unit ns ns ns ns ns tCK tCK tCK ns ns ns ns tCK ns ns ns ns ns tCK tCK tCK ns tCK tCK tCK tCK ns tCK ns ns ns ns 9 13 13 13 5,11 5,11 5,11 12 9 9 9 Notes 6 6,8 6,8 7 7 9 9 9 7 10 10 10 tAH Address hold time tAS Address setup time tBDL Last data-in to burst stop Read/write command to tCCD read/write command Last data-in to new tCDL column address delay tCH CLK high-level width tCK tCKED tCKH tCKS tCL tCMH tCMS tDAL CLK cycle time CKE to CLOCK disable or power-down entry mode CKE hold time CKE setup time CLK low-level width CS, RAS, CAS, WE, DQM hold time CS, RAS, CAS, WE, DQM setup time Data-in to ACTIVE command 3 2 1 7 tDH Data in hold time tDPL Data in to PRECHARGE tDQD DQM to input data delay DQM to data mask during tDQM writes DQM to data high Z tDQZ during reads tDS Data in setup time Write command to input tDWD data delay tHZ tLZ Data-out high-impedance time Data-out low-impedance time 5/21/01; v.1.1 Alliance Semiconductor P. 8 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Sym tMRD tOH tPED tRAS tRC tRCAR tRCD tREF tROH tRP tRRD tT tWR tXSR Parameter Load mode register to active/refresh command Output data hold time @ 30 pF CKE to CLOCK enable or power-down exit mode Active to precharge command Active command period Auto refresh period Active to read or write delay Refresh period--2048 rows Data-out high Z from precharge/burst stop command Precharge command period Active Bank A to Active Bank B command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command CAS latency -7 Min 2 Max - - - - - 120,000 - - - 64 - - - - - 1.0 - - Min 2 2.5 2.5 2.5 1 48 80 80 3 - 3 2 1 3 16 0.3 2 80 -8 Max - - - - - 120,000 - - - 64 - - - - - 1.0 - - Min 2 3 3 3 1 50 80 80 3 - 3 2 1 3 20 0.3 2 80 -10 Max - - - - - 120,000 - - - 64 - - - - - 1.0 - - Unit tCK ns ns ns tCK ns ns ns tCK ms tCK tCK tCK tCK ns ns tCK ns 20 9 9 9 8 8 Notes 5 6 6 6 3 2 1 2 2 2 1 42 70 70 3 3 - 8 3 2 1 3 3 2 1 3 14 0.3 2 70 Notes 1 IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 2 Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels. 3 Address transitions average one transition every two-clock period. 4 The IDD current will decrease as the CAS-latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS-latency is reduced. 5 tCK = 7 ns for -7, 8 ns for -8, and 10 ns for -10. 6 If clock tr > 1 ns, (tr/2 - 0.5)ns should be added to the parameter. 7 If clock (tr and tf) > 1 ns, [(tr + tf)/2 - 1] ns should be added to the parameter. 8 VIH overshoot: VIH(max) = VDDQ + 2V for a pulse width 3 ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL(min) = -2V for a pulse width 3 ns and the pulse width cannot be greater than one third of the cycle rate. 9 Required clocks are specified by JEDEC functionalisty and are not dependent on any timing parameter. 10 The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR and PRECHARGE commands). CKE may be used to reduce the data rate. 11 Timing actually specified tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 12 Timing actually specified by tWR. 13 tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going to HIGH-Z. 14 CLK must be toggled a minimum of two times during this period. 15 Enables on-chip refresh and address counters. 16 All voltages referenced to VSS. 17 The minimum specifications are used only to indicate the cycle time at which proper operation over the full temperature range (0 C TA 70 C) is endured. 5/21/01; v.1.1 Alliance Semiconductor P. 9 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) 18 A proper power-up initialization sequence (as described on page 10) is needed before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at the same potential.)Two AUTOREFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 19 AC characteristics assume tT = 1 ns. 20 In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 21 AC timing and IDD tests have VIL = 0V and VIH = 3.0 V with timing referenced to 1.4V crossover point. 22 IDD specifications are tested after the device is properly initialized. 23 Minimum clock cycles = (minimum time/clock cycle time) rounded up. Device operation Command Pin settings Description The following sequence is recommended prior to normal operation. 1 Apply power, start clock, and assert CKE and DQM high. All other signals are NOP. 2 After power-up, pause for a minimum of 200s. CKE/DQM = high; all others NOP. 3 Precharge both banks. 4 Perform Mode Register Set command to initialize mode register. 5 Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry. (Steps 4 and 5 may be interchanged.) The mode register stores the user selected opcode for the SDRAM operating modes. The CAS latency, burst length, burst type, test mode and other vendor specific functions are selected/programmed during the Mode Register Set command cycle. The default setting of the mode register is not defined after power-up. Therefore, it is recommended that the power-up and mode register set cycle be executed prior to normal SDRAM operation. Refer to the Mode Register Set table and timing for details. The SDRAM performs a "no operation" (NOP) when RAS, CAS, and WE = high. Since the NOP performs no operation, it may be used as a wait state in performing normal SDRAM functions. The SDRAM is deselected when CS is high. CS high disables the command decoder such that RAS, CAS, WE and address inputs are ignored. Device deselection is also considered a NOP. The SDRAM is configured with two internal banks. Use the Bank Activate command to select a row in one of the two idle banks. Initiate a read or write operation after tRCD(min) from the time of bank activation. Use the Burst Read command to access a consecutive burst of data from an active row in an active bank. Burst read can be initiated on any column address of an active row. The burst length, sequence and latency are determined by the mode register setting. The first output data appears after the CAS latency from the read command. The output goes into a high impedance state at the end of the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless output data stream. A full-page burst does not terminate automatically at the end of the burst. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write Power up Mode register set CS = RAS = CAS = WE = low; A0~A11 = opcode Device deselect and no operation CS = high, or RAS, CAS, WE = high Bank activation CS = RAS = low; CAS = WE = high; A0~A10 = row address; A11 = bank select Burst read CS = CAS = A10 = low; RAS = WE = high; A11 = bank select, A0~A8 = column address; (A9 = don't care for 2M x 8; A8, A9 = don't care for 1M x 16) 5/21/01; v.1.1 Alliance Semiconductor P. 10 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Command Pin settings CS = CAS = WE = A10 = low; RAS = high; A0~A9 = column address; (A9 = don't care for 2M x 8; A8, A9 = don't care for 1M x 16) Burst write UDQM/LDQM (x16) DQM (x8) operation CS = WE = low; RAS = CAS = high CS = A10 = RAS = WE = low; CAS = high; A11 = bank select; A0~A9 = don't care Burst stop Bank precharge Description Use the Burst Write command to write data into the SDRAM on consecutive clock cycles to adjacent column addresses. The burst length and addressing mode is determined by the mode register opcode. Input the initial write address in the same clock cycle as the Burst Write command. Burst terminate behavior for write is the same as that for read. Terminate the burst with a burst stop command, precharge command to the same bank or another burst read/write. DQM can also be used to mask the input data. Use DQM to mask input and output data. It disables the output buffers in a read operation and masks input data in a write operation. The output data is invalid 2 clocks after DQM assertion (2 clock latency). Input data is masked on the same clock as DQM assertion (0 clock latency). Use burst stop to terminate burst operation. This command may be used to terminate all legal burst lengths. The Bank Precharge command precharges the bank specified by A11. The precharged bank is switched from active to idle state and is ready to be activated again. Assert the precharge command after tRAS(min) of the bank activate command in the specified bank. The precharge operation requires a time of tRP(min) to complete. CS = RAS = WE = low; CAS = The Precharge All command precharges both banks simultaneously. A10 = high; A11, A0~A9 = Both banks are switched to the idle state on precharge completion. don't care During auto precharge, the SDRAM adjusts internal timing to satisfy t (min) and tRP for the programmed CAS latency and burst length. Write: CS = CAS = WE = low ; RAS Couple the auto precharge with a burst read/write operation by Read: CS = CAS = low; asserting A10 to a high state at the same time the burst read/write A10 = high; A11 = bank select; commands are issued. At auto precharge completion, the specified Auto precharge A0~A9 = column address; bank is switched from active to idle state. Note that no new commands (A9 = don't care for 2M x 8; A8, (RD/WR/DEAC) can be issued to the same bank until the specified A9 = don't care for 1M x 16) bank achieves the idle state. Auto precharge does not work with fullpage burst. When CKE is low, the internal clock is frozen or suspended from the next clock cycle and the state of the output and burst address are frozen. If both banks are idle and CKE goes low, the SDRAM enters Clock suspend/power power down mode at the next clock cycle. When in power down CKE = low down mode entry mode, no input commands are acknowledged as long as CKE remains low. To exit power down mode, raise CKE high before the rising edge of CLK. Resume internal clock operation by asserting CKE high before the Clock suspend/power CKE = high rising edge of CLK. Subsequent commands can be issued one clock down mode exit cycle after the end of the Exit command. Precharge all 5/21/01; v.1.1 Alliance Semiconductor P. 11 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Command Pin settings Auto refresh CS = RAS = CAS = low; WE = CKE = high; A0~A11 = don't care Self refresh CS = RAS = CAS = CKE = low; WE = high; A0~A11 = don't care Description SDRAM storage cells must be refreshed every 64 ms to maintain data integrity. Use the auto refresh command to accomplish the refreshing of all rows in both banks of the SDRAM. The row address is provided by an internal counter which increments automatically. Auto refresh can only be asserted when both banks are idle and the device is not in the power down mode. The time required to complete the auto refresh operation is tRC(min). Use NOPs in the interim until the auto refresh operation is complete. Both banks will be in the idle state after this operation. Self refresh is another mode for refreshing SDRAM cells. In this mode, refresh address and timing are provided internally. Self refresh entry is allowed only when both banks are idle. The internal clock and all input buffers with the exception of CKE are disabled in this mode. Exit self refresh by restarting the external clock and then asserting CKE high. NOPs must follow for a time of tRC(min) for the SDRAM to reach the idle state where normal operation is allowed. If burst auto refresh is used in normal operation, burst 2048 auto refresh cycles immediately after exiting self refresh. Initialize and load mode register T0 T1 tCK tCKS tCKH Tn tCH CLK CKE tCMH tCL Tm Tp+1 Tp+2 Tp+3 tCMS PRECHARGE ALL COMMAND DQM* NOP AUTO REFRESH NOP NOP AUTO REFRESH NOP NOP LOAD MODE REGISTER NOP ACTIVE tAS tAH CODE BANK ROW ADDRESS High Z A10=HIGH DQ T=200s (min) tRP tRCAR tMRD Power up: VDD and CLK stable. Precharge all banks. (8 AUTO REFRESH CYCLES) AUTO REFRESH Program Mode Register * DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. The Mode Register may be loaded prior to the auto refresh cycles if desired. Outputs are guaranteed High-Z after command is issued. 5/21/01; v.1.1 Alliance Semiconductor P. 12 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Read--DQM operation* T0 CLK tCKS tCKH tCK* T1 tCL T2 tCH T3 tCL T4 T5 T6 T7 T8 CKE tCMS tCMH NOP READ tCMS tCMH tDQZ tAS tAH Column m (A0-A7)3 COMMAND DQM A0-A9 A10 BA DQ ACTIVE NOP NOP NOP NOP NOP NOP ROW tAS tAS tAH tAH ROW ENABLE AUTOPRECHARGE ROW DISABLE AUTOPRECHARGE BANK BANK tAC* tLZ tOH DOUT m tHZ tLZ tAC* tAC* tOH DOUT m+2 tOH DOUT m+3 tHZ tRCD CAS latency * For this example, the burst length = 4, and the CAS latency = 2. A8 and A9 = "Don't care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Write--DQM operation* T0 CLK tCKS tCKH tCK* T1 tCL T2 tCH T3 T4 T5 T6 T7 CKE tCMS tCMH NOP WRITE tCMS tCMH NOP NOP NOP NOP NOP COMMAND DQM ACTIVE tAS tAH Column m (A0-A7) ENABLE AUTOPRECHARGE DISABLE AUTOPRECHARGE BANK A0-A9 A10 BA DQ * ROW tAS tAS tAH tAH ROW BANK tDS tRCD tDH DIN m tDS tDH tDS tDH DIN m+2 DIN m+3 For this example, the burst length = 4. A8 and A9 = "Don't care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. 5/21/01; v.1.1 Alliance Semiconductor P. 13 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Write--full-page burst T0 CLK tCKS tCKH tCL T1 tCH tCK* T2 T3 T4 T5 Tn+1 Tn+2 Tn+3 CKE tCMS tCMH NOP WRITE tCMS tCMH NOP NOP NOP NOP BURST TERM NOP COMMAND DQM ACTIVE tAS tAH Column m (A0-A7)* A0-A9 A10 BA DQ ROW tAS tAS tAH tAH ROW BANK tDS tRCD BANK tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH DIN m D IN m+1 DIN m+2 DIN m+3 DIN m+255 256 locations within same row Full page completed Full-page burst does not self terminate. Can use BURST TERMINATE command. * A8 and A9 = Don't care. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. Page left open; no t . RP Read--full-page burst* T0 tCL T1 tCK tCH tCMS tCMH T2 T3 T4 T5 T6 Tn+1 Tn+2 Tn+3 Tn+4 CLK CKE tCMS tCMH ACTIVE NOP READ NOP NOP NOP NOP NOP Command DQM tAS tAH ROW tAS tAH COLUMNm (A0-A7) BURST TERM NOP NOP A0-A9 A10 tAS ROW tAH BANK BANK tAC* tAC* tOH DOUT m BA tAC* tOH DOUT m+1 tAC* tOH DOUT m+2 tAC* tOH DOUT m+255 tAC* tOH DOUT m tOH DOUT m+1 DQ tRCD tLZ CAS Latency 256 locations within same row Full page completed tHZ* Full-page burst does not self-terminate. ** Can use BURST TERMINATE command. * For this example, the CAS latency = 2. A8 and A9 = "Don't care." DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte. ** Page left open; no t . RP 5/21/01; v.1.1 Alliance Semiconductor P. 14 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Mode register set command waveform CLK CMD PRE Or Auto Refresh tRP MRS tRSC(min) tMRD ACT MRS can be issued only when both banks are idle. Precharge waveforms Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP . The earliest assertion of the precharge command without losing any burst data is show below. (normal write; BL = 4) CLK CMD DQ WE PRE D0 D1 D2 D3 (normal read; BL = 4) CLK CMD DQ(CL1) DQ(CL2) DQ(CL3) Read data PRE Q0 Q1 Q2 Q3 Q0 Q1 Q0 Q2 Q1 Q3 Q2 Q3 Auto precharge waveforms A10 controls the selection of auto precharge during the read or write command cycle. (write with auto precharge; BL = 4) CLK CMD DQ WE D0 D1 D2 D3 Auto precharge starts* (read with auto precharge; BL = 4) CLK CMD DQ(CL1) DQ(CL2) DQ(CL3) Read data Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Auto precharge starts* *The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of another activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal. 5/21/01; v.1.1 Alliance Semiconductor P. 15 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) DQM waveforms: CLK CMD DQM tDQZ Read data read (CL = 3, BL = 4) DQ(CL = 3) DQ(CL = 2) Q0 tDQZ Q0 Q1 Q2 Q3 DQM waveforms: CLK CMD Ext DIN DQM Data written D0 D1ignored D2 ignored D3 Write data write (BL = 4) D0 D1 D2 D3 Concurrent Auto-P Waveforms According to IntelTM's specification, auto-p burst interruption is allowed by another burst provided that the interrupting burst is in a different bank than the ongoing burst. (A) RD-P interrupted by RD in another bank CLK CMD DQ RD-P(A) RD (B) (CL = 3, BL = 4) A0 tRP(A) Bank A precharge starts A1 B0 B1 B2 B3 (B) RD-P interrupted by WR in another bank CLK CMD DQM DQ QA0 QA1 DN(B0) D(B1) tRP Bank A precharge starts D(B2) RD-P (A) WR (B) (CL = 3, BL = 8) D(B7) 5/21/01; v.1.1 Alliance Semiconductor P. 16 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) (C) WR-P interrupted by RD in another bank CLK CMD DQ WRP (A) RD (B) (CL = 2, BL = 4) D(A0) D(A1) QB0 tRP Bank A precharge starts QB1 QB2 QB3 (D) WR-P Interrupted by WR in another bank CLK Bank A precharge starts (CL = 3, BL = 4) CMD DQ WRP (A) WR (B) DA0 DA1 DA2 DB0 DB1 DB2 DB3 Clock suspension read waveforms CLK external CLK internal CKE (BL = 8) DQM DQ CLK external CLK internal CKE DQM DQ Q1 Q2 tCKED Q3 tPED Q4 Q6 Q1 Q2 Q3 Q4 OPEN OPEN Q6 Q7 CLK external CLK internal CKE DQM DQ Q1 Q2 Q3 Q4 Q5 Q6 5/21/01; v.1.1 Alliance Semiconductor P. 17 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Clock suspension write waveforms CLK external CLK internal CKE DQM DQ D1 D2 D3 DQM Mask D5 CKE Mask D6 tCKH tCKS CLK external CLK internal CKE DQM DQ D1 D2 D3 DQM Mask CKE Mask D5 D6 CLK external CLK internal CKE DQM DQ D1 D2 D3 CKE Mask D4 D5 D6 tCMS tCMH Read/write interrupt timing CLK CMD ADD DQ (CL1) DQ (CL2) DQ (CL3) tCCD tCMS tCMH Read data Read data read interrupted by read (BL = 4) A B QA0 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 tCCD = CAS to CAS delay (= 1 CLK). 5/21/01; v.1.1 Alliance Semiconductor P. 18 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) write interrupted by write (BL = 4) tCK tCL tCH CLK tCCD CMD ADD DQ Write data Write data A0 B0 DA0 tDS tDH tCDL DB0 DB1 DB2 DB3 tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). write interrupted by read (BL = 4) CLK tCCD CMD ADD DQ (CL1) DQ (CL2) DQ (CL3) Write data Read data A B DA0 QB0 QB1 QB0 QB2 QB1 QB3 QB2 QB3 DA0 DA0 tCDL QB0 QB1 QB2 QB3 tCCD = CAS to CAS delay (= 1 CLK). tCDL = last address in to new column addres delay (= 1 CLK). Interrupting RD/WR can be for either the same or different banks. read interrupted by write (CL = 1, BL = 4) CLK CMD1 DQM1 DQ1 tLZ tHZ Read data D0 D1 D2 D3 Read data Write data CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 Write data D0 D1 D2 D3 Read data Write data Q0 Q1 D0 D1 D2 D3 To prevent bus contention, maintain a gap between data in and data out. 5/21/01; v.1.1 Alliance Semiconductor P. 19 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) read interrupted by write (CL = 2, BL = 4) CLK CMD1 DQM1 DQ1 CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 CMD4 DQM4 DQ4 Q0 D0 D1 D2 D3 Read data D0 D1 Write data D2 D3 Read data D0 D1 Write data D2 D3 Read data D0 D1 Write data D2 D3 Read data Write data To prevent bus contention, maintain a gap between data in and data out. read interrupted by write (CL = 3, BL = 4) CLK CMD1 DQM1 DQ1 CMD2 DQM2 DQ2 CMD3 DQM3 DQ3 CMD4 DQM4 DQ4 To prevent bus contention, maintain a gap between data in and data out. D0 D1 D2 D3 Read data D0 D1 Write data D2 D3 Read data Read data D0 D1 Write data D2 D3 Read data tCCD Write data D0 D1 Write data D2 D3 Burst termination Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously. 5/21/01; v.1.1 Alliance Semiconductor P. 20 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Burst stop command waveform tT CLK CMD DQ (CL = 1) DQ (CL = 2) DQ (CL = 3) Read data Burst stop read cycle tOH Q0 Q1 Q2 Q0 Q1 Q2 Q0 Q1 Q2 write cycle (BL = 8) CLK CMD DQ (CL = 1,2,3) Write data Burst stop DQ D1 D2 D3 Precharge termination A Precharge command terminates a burst read/write operation during the read cycle. The same bank can be activated after meeting tRP. If an RD-burst is terminated, o/p will go to High Z after the number of cycles = CAS latency. read cycle (CL = 1) CLK CMD DQ Read data PRE Q0 Q1 Q2 Q3 tRP ACT read cycle (CL = 2) tRP CLK CMD DQ Read data Q0 Q1 PRE Q2 Q3 tROH (CL = 2) ACT read cycle (CL = 3) CLK CMD DQ Read data PRE tRP ACT Q0 Q1 Q2 tROH (CL = 3) Q3 5/21/01; v.1.1 Alliance Semiconductor P. 21 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) write cycle tWR CLK CMD DQ Write data PRE ACT D0 D1 D2 D3 Q4 tRP Write recovery tDPL (BL = 4) CLK CMD DQ tRP Write data PRE tDAL D0 D1 D2 D3 ACT This precharge is implicit in case of Auto-P Write. Auto refresh waveform CLK tRP CS RAS CAS WE A10 A0-A9 DQM CKE DQ Precharge both banks Auto refresh tRC tRC Auto refresh Auto refresh 5/21/01; v.1.1 Alliance Semiconductor P. 22 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Self refresh waveform CLK CS RAS CAS WE A11 A0-A10 DQM CKE DQ Self refresh Precharge both banks Self refresh entry cycle tRC Self refresh exit Clock stable before self refresh exit Arbitrary cycle Power down mode waveform CLK CS RAS CAS WE A11 A10 A0-A9 DQM CKE DQ Bank activate Active standby Power down mode NOP RAa RAa (CL = 3) RAa CAa RAa CAx Data burst Precharge standby Power down mode NOP Bank activate Power down mode entry Power down mode exit Power down mode entry Power down mode exit Enter power down mode by pulling CKE low. All input/output buffers (except CKE buffer) are turned off in power down mode. When CKE goes high, command input must be equal to no operation at next CLK rising edge. 5/21/01; v.1.1 Alliance Semiconductor P. 23 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Read/write waveform CLK tRAS (BL = 8, CL = 3) CS RAS CAS WE A11 tRCD A10 A0-A9 DQM CKE DQ RAa RAa CAa CAb RAb RAb tRP Aa0 Aa1 Aa2 Aa3 Aa4 Aa5 Ab0 Ab1 Ab2 Ab3 Ab4 Ab5 Bank activate Read Q Q Q Q Q Q D Write D D D D D Bank activate Precharge Burst read/single write waveform CLK CS RAS CAS WE A11 A10 A9 DQM CKE DQ Activate Read Aa0 Aa1 Aa2 Aa3 Ab Ac Ad0 Ad1 RAa (BL = 4, CL = 3) RAa CAa CAb CAc CAd Ad2 Ad3 Q Q Q Q D Single Write D Read Q Q Q Q 5/21/01; v.1.1 Alliance Semiconductor P. 24 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Interleaved bank read waveform CLK tCCD tCCD tCCD (BL = 4, CL = 3) CS tRAS RAS CAS WE A11 tRCD tRCD RBa CAa RBa tRAS CAb CBb A10 A0-A9 DQM CKE DQ Bank A: Bank B: RAa RAa CBa CAc QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 QAb0 QAb1 QAb2 QAc0 QAc1 QAc2 QBb0 QBb1 QBb2 QBb3 Active Read Active Read Read Precharge Read Read Precharge Interleaved bank read waveform CLK CS tRC tRC (BL = 4, CL = 3, Autoprecharge) RAS tRAS tRP tRAS tRAS tRP tRP CAS WE A11 tRCD tRCD RBb tRCD RAc RBd A10 A9 DQM CKE RAa RAa CAa RBb CBb RAc CAc RBd tRRD tRRD QAa0 QAa1 QAa2 QAa3 tRRD QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAc2 QAc3 DQ Bank A: Bank B: Active Read Active AP Active Read Read AP Active AP AP = internal precharge begins 5/21/01; v.1.1 Alliance Semiconductor P. 25 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Interleaved bank read waveform CLK CS tRC (BL = 8, CL = 3) RAS tRAS tRP tRAS tRP CAS WE A11 A10 A9 DQM CKE DQ Bank A: Bank B: Active Read Precharge Active Read QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QBb0 QBb1 QBb4 QBb5 QBb6 QBb7 QAc0 QAc1 tRCD RAa RBb tRCD RAc tRCD RAa CAa RBb CBb RAc CAc Precharge Active Read Precharge Interleaved bank read waveform CLK CS RAS tRAS tRP tRAS tRC (BL = 8, CL = 3, Autoprecharge) CAS WE A11 tRCD tRCD RBb RAc RAc tRCD A10 A9 DQM CKE DQ RAa RAa CAa RBb CAb CAc QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 QBb0 QBb1 tRRD QBb4 QBb5 QBb6 QAc0 QAc0 Bank A Active Bank B AP = internal precharge begins Read tRRD Active AP Read Active Read AP 5/21/01; v.1.1 Alliance Semiconductor P. 26 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Interleaved bank write waveform CLK CS RAS tRAS tRC (BL = 8) tRP tRAS CAS tRCD tRCD tRCD WE A11 A10 A9 DQM CKE DQ Bank A Active Bank B DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 RAa RBb RAc RAa CAa RBb CAb RAc CAc Write Active Write Precharge Active Write Precharge Interleaved bank write CLK CS tRC (BL = 8, Autoprecharge) RAS tRAS tRP tRAS CAS WE tRCD tRCD tRCD A11 A10 A9 DQM CKE DQ Bank A Active Bank B AP = internal precharge begins DAa0 DAa1 DAa4 DAa5 DAa6 DAa7 DBb0 DBb1 DBb2 DBb3 DBb4 DBb5 DBb6 DBb7 DAc0 DAc1 DAc2 RAa RBb RAc RAc RAa CAa RBb CAb CAc Write Active Write AP Bank A Active Write AP Bank B 5/21/01; v.1.1 Alliance Semiconductor P. 27 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Package dimensions 50 494847 4645 444342 4140 393837 36 35343332 3130 29 28 2726 c 44-pin TSOP 2 Min (mm) Max (mm) 1.2 - 1.05 0.45 18.54 10.29 11.96 0.60 50-pin TSOP 2 Min (mm) 0.05 0.95 0.30 0.12 20.85 10.03 11.56 0.40 1.05 0.45 0.21 21.05 10.29 11.96 0.60 Max (mm) 1.2 TSOP 2 E He A A1 A2 b - 0.05 0.95 0.30 18.28 10.03 11.56 0.40 1 2 3 4 5 6 7 8 9 1011 12 13 14 1516171819 20 21 2223 2425 D l c D E He e 0-5 0.127 (typical) A A1 b e A2 0.80 (typical) 0.80 (typical) l AC test conditions - Output reference levels = 1.4V - Input rise and fall times: 2 ns DOUT CLOAD = 50 pF Figure A: Equivalent output load +1.5V 50 Capacitance 15 Parameter Input capacitance I/O capacitance Symbol CIN1 CIN2 CI/O Signals = 1 MHz, Ta = 25 C, VCC = 3.3V Max 4 4 5 Unit pF pF pF A0 to A11 DQM, RAS, CAS, WE, CS, CLK, CKE, DQ0 to DQ7 (2M x 8) DQ0 to DQ15 (1M x 16) Ordering information Package \1/ frequency TSOP 2, 400 mil, 44-pin TSOP 2, 400 mil, 44-pin TSOP 2, 400 mil, 50-pin TSOP 2, 400 mil, 50-pin -7 ns AS4LC2M8S1-7TC AS4LC2M8S0-7TC AS4LC1M16S1-7TC AS4LC1M16S0-7TC -8 ns AS4LC2M8S1-8TC AS4LC2M8S0-8TC AS4LC1M16S1-8TC AS4LC1M16S0-8TC -10 ns AS4LC2M8S1-10TC AS4LC2M8S0-10TC AS4LC1M16S1-10TC AS4LC1M16S0-10TC 5/21/01; v.1.1 Alliance Semiconductor P. 28 of 29 AS4LC2M8S1 AS4LC1M16S1 (R) Part numbering system AS4 LC XXX SX -XX T Package (device dependent): TSOP 2 400 mil, 44 pin TSOP 2 400 mil, 50 pin C Commercial temperature range: 0 C to 70 C Device number S1 = 2K refresh DRAM prefix 3.3V CMOS for synchronous 1/frequency S0 = 4K refresh DRAM 5/21/01; v.1.1 Alliance Semiconductor P. 29 of 29 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. 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